The RCW directories names for the LS2088ARDB boards conform to the following naming convention: abcdefgh_ij_kl_mn: a = What is available in SFP cage 1 b = What is available in SFP cage 2 c = What is available in SFP cage 3 d = What is available in SFP cage 4 e = What is available in SFP cage 5 f = What is available in SFP cage 6 g = What is available in SFP cage 7 h = What is available in SFP cage 8 i = What is available in Slot 1 j = What is available in Slot 2 k = SATA1 l = SATA2 For the Slots (c..j): 'N' is NULL, not available/not used 'P' is PCIe 'S' is SGMII 'Q' if QSGMII 'F' is XFI 'H' is SATA Serdes1 protocol (m): m = 'hex value of serdes1 protocol value' Serdes2 protocol (n): n = 'hex value of serdes2 protocol value' BIN Core/Platform/DDR Bin1: 1800MHz/700MHz/1866MT/s Ref clock setting on board ========================== DDR Ref clock: 133.33MHz Sys PLL Ref clock: 100MHz Files naming convention ============================= rcw_x.rcw rcw_x_y.rcw rcw_x_bootmode.rcw x = Core frequency y = Platform frequency bootmode = nor(default)/sd/qspi For example, rcw_2000.rcw means rcw for core frequency of 2000MHz. rcw_2000_700.rcw means rcw for core frequency 2000MHz and Platform frequecny 700MHz. rcw_2000_qspi.rcw means rcw for core frequency of 2000MHz with QSPI boot. Errata Workaround Implemented ============================= A-010679: RCW[7] must be set to 1 to enable SYS_PLL_FB (Only required for Rev1.0) A-009102: Default SERDES setting may cause excess errors in SATA controller Workaround: Write 0x502880 to LNmSSCR1 register for every lane before enabling SATA operation.Using PBI commands write 0x802880 to 0x01eb099c write 0x802880 to 0x01eb09dc A-010554: SATA controller may fail to detect some hard drives Workaround: Before enabling SATA controller write 0x80104e20 to 0x1eb1300 write 0x80104e20 to 0x1eb1310 A-000009: SATA Gen3 speed (6Gbps) exhibit high error rate Workaround: Before enabling SATA controller write 0x00502880 to 0x1eb099c write 0x00502880 to 0x1eb09dc A-008851: Invalid transmitter/receiver preset values are used in Gen3 equalization phases during link training for RC mode This errata is valid only for PCI gen3. Workaround: write 0x00000001 to MISC_CONTROL_1_OFF write 0x4747 to Lane Equalization Control register for each lane For 0x2a_0x3f: write 0x00000001 to 0x036008bc write 0x47474747 to 0x03600164 write 0x47474747 to 0x03600168 write 0x00000001 to 0x037008bc write 0x47474747 to 0x03700154 write 0x47474747 to 0x03700158 write 0x00800401 to 0x03600890 write 0x00800401 to 0x03700890 A-010160: PBI command "CRC and STOP" is not functional for devices with NSEC fuse blown to 1 Workaround: For non-secure devices, use the "STOP" command instead of the "CRC and STOP" command to terminate PBI. Single RCW is maintained for secure and non-secure devices for LS2088 platforms and "STOP" command is used instead of "CRC and STOP" command, so this issue is not faced. This support is implemented using 'nocrc' flag in python script, which indicates to use "STOP" command instead of "CRC and STOP". 'nocrc' flag can be enabled for required platforms.