The RCW directories names for the LS1028AQDS boards conform to the following
naming convention:

ab_cdef_g:

a = 'R' indicates RGMII1@DTSEC3 is supported
b = 'R' indicates RGMII2@DTSEC4 is supported
    'N' indicates not available/not used

c = What is available in Slot 1 or SPF cage
d = What is available in Slot 2
e = What is available in Slot 3
f = What is available in Slot 4

For the Slots (c..f):
 'N' is NULL, not available/not used
 'P' is PCIe
 'X' is XAUI
 'S' is SGMII
 'Q' if QSGMII
 'F' is XFI
 'H' is SATA
 'A' is AURORA

For the srds_prtcl (g):
g = 'hex value of serdes1 protocol value'

So RR_FQPP_1455 means:
 - RGMII1@DTSEC3 on board
 - RGMII2@DTSEC4 on board
 - XFI on SFP cage
 - QSGMII on Slot 2
 - PCIe2 on Slot 3
 - PCIe3 on Slot 4
 - SERDES1 Protocol is 0x1455

BIN   Core/Platform/FMan/DDR
Bin1: 1500MHz/400MHz/500MHz/1600MT/s
Bin2: 1400MHz/300MHz/500MHz/1600MT/s
Bin3: 1200MHz/300MHz/500MHz/1300MT/s

Files naming convention
=============================
rcw_x.rcw
rcw_x_bootmode.rcw
rcw_x_specialsetting.rcw
x = Core frequency
bootmode = bootmode:SD/NAND/NOR and so on.
specialsetting = special setting:
			lpuart:used for lpuart
			sben:Secure boot
For example,
	rcw_1600.rcw means rcw for core frequency of 1600MHz with nor boot.

	rcw_1600_sd.rcw means rcw for core frequency of 1600MHz with sd boot.

For more information please refer to the comments in rcw file.

Pin configuration
============================
1. Enable audio support, set the following in rcw:
	EC1_SAI4_5_PMUX=2

2. Disable serdes support, set the following in rcw:
	SRDS_PLL_PD_PLL1=1
	SRDS_PLL_PD_PLL2=1
	SRDS_PRTCL_S1_L0=0
	SRDS_PRTCL_S1_L1=0
	SRDS_PRTCL_S1_L2=0
	SRDS_PRTCL_S1_L3=0

Errata Workaround Implemented
=============================
A-008851:
	Invalid transmitter/receiver preset values are used in Gen3 equalization
	phases during link training for RC mode
	This errata is valid only for PCI gen3.
	Workaround:
		write 0x00000001 to MISC_CONTROL_1_OFF
		write 0x4747 to Lane Equalization Control register for each lane
	For 0xcccc:
		write 0x00000001 to 0x034008bc
		write 0x47474747 to 0x03400154
		write 0x47474747 to 0x03400158
		write 0x00000001 to 0x035008bc
		write 0x47474747 to 0x03500154
		write 0x47474747 to 0x03500158

A-010477:
	The PCI Express controller may not be able to establish the link at Gen3
	speed successfully with some Gen3-capable link partner. The link will be
	down-trained to either Gen1 or Gen2 speed.
	Workaround:
		Write 0x00800401 to GEN3 Control Register (GEN3_RELATED_OFF)
	For 0xcccc:
		write 0x00800401 to 0x03400890
		write 0x00800401 to 0x03500890